1. Field of the Invention
The present invention relates to a method of forming trench capacitor and memory cell, and more particularly, to a method that uses a low grade photo mask to form the deep trench in the trench capacitor and the memory cell.
2. Description of the Prior Art
Dynamic Random Access Memory (DRAM) is an integrated circuit formed by many memory cells and a prominent volatile memory for the time being. As electrical products tend towards increasing miniaturization, DRAM devices need to have a high integration and density. Trench capacitor DRAM devices are popularly used for high density DRAM that is formed in a deep trench capacitor of the semiconductor substrate to effectively decrease the size of memory unit and efficiently utilize the space of the chip.
Please refer to FIGS. 1-3, wherein FIG. 1 is the plain view and FIGS. 2-3 are the schematic cross-sectional views illustrating the forming for trench capacitors in prior art. FIG. 2 is a cross-sectional diagram along the line 2-2′ of the substrate shown in FIG. 1. As indicated, the conventional method for forming the trench capacitors 10 are firstly to form a patterned photoresist (not shown) on a silicon substrate 100 on which has a hard mask layer 104 defining the positions for a plurality of the trench capacitors 10. Then a photo mask pattern transferring process is performed to form a plurality of openings 102 in the hard mask layer 104 to define the plurality of the trench capacitors 10. The openings 102 in the hard mask layer 102 are used for etching a plurality of deep trenches in the silicon substrate 100. Then diffusion regions 106, a capacitor dielectric 108, and capacitor bottom electrodes 110 are sequentially formed to complete the forming of a trench capacitor. Additionally, the diffusion region 106 is used as the buried electrode in the trench capacitor 10.
Next, as shown in FIG. 3, by using the etching, deposition, chemical mechanical polish (CMP), ion implanting processes, a plurality of shallow trench isolations (STIs) 202 are formed in any two adjacent trench capacitors 10 along with the corresponding gates 204, spacers 206, and source/drain 208. At last an optional salicide process is performed. The trench capacitors 10 are electrically connected to other devices and metal interconnection by a plurality of contact plug (not shown).
However, the conventional method described above involves using a photo mask having a pattern to define the trench capacitor array in the photoresist and the hard mask as shown in FIG. 1. Then the substrate is etched to form the deep trenches according to the patterned transferred from the photo mask. And another photo mask having the pattern of STI array is required to form the STIs in any two adjacent capacitors. In other words, not only the two photo mask require for high density and accurate alignment in X direction and Y direction, which increases the possibility of fail in exposure, development, and etching process, but also the trench capacitors' electrical performance may be influenced because the diffusion region and the capacitor bottom electrode are easily damaged and contaminated during the etching, cleaning, CMP processes performed for forming STIs.